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1 3.3 volt cmos syncfifo? 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 idt72v201, idt72v211 idt72v221, idt72v231 idt72v241, idt72v251 ? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. dsc-4092/4 february 2006 idt and the idt logo are trademarks of integrated device technology, inc. syncfifo is a trademark of integrated device technolo gy, inc. commercial and industrial temperature ranges are very high-speed, low-power first-in, first-out (fifo) memories with clocked read and write controls. the architecture, functional operation and pin assignments are identical to those of the idt72201/72211/72221/72231/ 72241/72251, but operate at a power supply voltage (vcc) between 3.0v and 3.6v. these devices have a 256, 512, 1,024, 2,048, 4,096 and 8,192 x 9-bit memory array, respectively. these fifos are applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. these fifos have 9-bit input and output ports. the input port is controlled by a free-running clock (wclk), and two write enable pins ( wen1 , wen2). data is written into the synchronous fifo on every rising clock edge when the write enable pins are asserted. the output port is controlled by another clock pin (rclk) and two read enable pins ( ren1 , ren2 ). the read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual- clock operation. an output enable pin ( oe ) is provided on the read port for three-state control of the output. the synchronous fifos have two fixed flags, empty ( ef ) and full ( ff ). two programmable flags, almost-empty ( pae ) and almost-full (paf), are provided for improved system control. the programmable flags default to empty+7 and full-7 for pae and paf , respectively. the programmable flag offset loading is controlled by a simple state machine and is initiated by asserting the load pin ( ld ). these fifos are fabricated using idt's high-speed submicron cmos technology. features: ? ? ? ? ? 256 x 9-bit organization idt72v201 ? ? ? ? ? 512 x 9-bit organization idt72v211 ? ? ? ? ? 1,024 x 9-bit organization idt72v221 ? ? ? ? ? 2,048 x 9-bit organization idt72v231 ? ? ? ? ? 4,096 x 9-bit organization idt72v241 ? ? ? ? ? 8,192 x 9-bit organization idt72v251 ? ? ? ? ? 10 ns read/write cycle time ? ? ? ? ? 5v input tolerant ? ? ? ? ? read and write clocks can be independent ? ? ? ? ? dual-ported zero fall-through time architecture ? ? ? ? ? empty and full flags signal fifo status ? ? ? ? ? programmable almost-empty and almost-full flags can be set to any depth ? ? ? ? ? programmable almost-empty and almost-full flags default to empty+7, and full-7, respectively ? ? ? ? ? output enable puts output data bus in high-impedance state ? ? ? ? ? advanced submicron cmos technology ? ? ? ? ? available in 32-pin plastic leaded chip carrier (plcc) and 32-pin plastic thin quad flatpack (tqfp) ? ? ? ? ? industrial temperature range (?40 c to +85 c) is available ? ? ? ? ? green parts available, see ordering information description: the idt72v201/72v211/72v221/72v231/72v241/72v251 syncfifos? functional block diagram wclk wen1 wen2 d 0 - d 8 ld offset register input register ram array 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 write control logic write pointer reset logic output register oe rs q 0 - q 8 rclk ren1 ren2 read control logic read pointer flag logic ef pae paf ff 4092 drw 01
idt72v201/72v211/72v221/72v231/72v241/72v251 3.3v cmos syncfifo? 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 commercial and industrial temperature ranges commercial and industrial temperature ranges february 8, 2006 2 temperature ranges symbol name i/o description d 0 -d 8 data inputs i data inputs for a 9-bit bus. rs reset i w hen rs is set low, internal read and write pointers are set to the first location of the ram array, ff and paf go high, and pae and ef go low. a reset is required before an initial write after power-up. wclk write clock i data is written into the fifo on a low-to-high transition of wclk when the write enable(s) are asserted. wen1 write enable 1 i if the fifo is configured to have programmable flags, wen1 is the only write enable pin. when wen1 is low, data is written into the fifo on every low-to-high transition wclk. if the fifo is configured to have two write enables, wen1 must be low and wen2 must be high to write data into the fifo. data will not be written into the fifo if the ff is low. wen2/ ld write enable 2/ i the fifo is configured at reset to have either t wo write enables or programmable flags. if wen2/ ld load is high at reset, this pin operates as a second write enable. if wen2/ ld is low at reset, this pin operates as a control to load and read the programmable flag offsets. if the fifo is configured to have two write enables, wen1 must be low and wen2 must be high to write data into the fifo. data will not be written into the fifo if the ff is low. if the fifo is configured to have programmable flags, wen2/ ld is held low to write or read the programmable flag offsets. q 0 -q 8 data outputs o data outputs for a 9-bit bus. rclk read clock i data is read from the fifo on a low-to-high transition of rclk when ren1 and ren2 are asserted. ren1 read enable 1 i when ren1 and ren2 are low, data is read from the fifo on every low-to-high transition of rclk. data will not be read from the fifo if the ef is low. ren2 read enable 2 i when ren1 and ren2 are low, data is read from the fifo on every low-to-high transition of rclk. data will not be read from the fifo if the ef is low. oe output enable i w hen oe is low, the data output bus is active. if oe is high, the output data bus will be in a high-impedance state. ef empty flag o when ef is low, the fifo is empty and further data reads from the output are inhibited. when ef is high, the fifo is not empty. ef is synchronized to rclk. pae programmable o when pae is low, the fifo is almost-empty based on the offset programmed into the fifo. the default almost-empty flag offset at reset is empty+7. pae is synchronized to rclk. paf programmable o when paf is low, the fifo is almost-full based on the offset programmed into the fifo. the default almost-full flag offset at reset is full-7. paf is synchronized to wclk. ff full flag o when ff is low, the fifo is full and further data writes into the input are inhibited. when ff is high, the fifo is not full. ff is synchronized to wclk. v cc power one 3.3v volt power supply pin. gnd ground one 0 volt ground pin. tqfp (pr32-1, order code: pf) top view plcc (j32-1, order code: j) top view pin configuration rs wen1 wclk wen2/ ld v q 8 q 7 q 6 q 5 5 6 7 8 16 cc d 1 paf pae gnd ren1 rclk ren2 d 0 27 26 25 24 23 22 21 29 28 32 31 30 9 101112131415 d d d d d 2 3 4 5 6 d d 7 8 4092 drw02 q 3 q 4 q 2 q 1 q 0 ef oe ff 1 2 3 4 20 19 18 17 index rs wen1 wclk wen2/ ld v cc q 8 q 7 q 6 q 5 5 6 7 8 9 10 11 12 13 d 1 paf pae gnd ren1 rclk ren2 oe d 0 27 26 25 24 23 22 21 29 28 432 1 32 31 30 14 15 16 17 18 19 20 d 2 d 3 d 4 d 5 d 6 d 7 d 8 q 3 q 4 q 2 q 1 q 0 ff ef index 4092 drw02a pin descriptions
3 idt72v201/72v211/72v221/72v231/72v241/72v251 3.3v cmos syncfifo? 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 commercial and industrial temperature ranges february 8, 2006 idt72v201 idt72v211 idt72v221 idt72v231 idt72v241 idt72v251 commercial and industrial (1) t clk = 10, 15, 20 ns symbol parameter min. typ. max. unit i li (2) input leakage current (any input) ?1 ? 1 a i lo (3) output leakage current ?10 ? 10 a v oh output logic ?1? voltage, i oh = ?2ma 2.4 ? ? v v ol output logic ?0? voltage, i ol = 8ma ? ? 0.4 v i cc1 (4,5,6) active power supply current ? ? 20 ma i cc2 (4,7) standby current ? ? 5 ma capacitance (t a = +25 c, f = 1.0mhz) symbol parameter conditions max. unit c in (2) input capacitance v in = 0v 10 pf c out (1,2) output capacitance v out = 0v 10 pf notes: 1. with output deselected ( oe v ih ). 2. characterized values, not currently tested. dc electrical characteristics (commercial: v cc = 3.3v 0.3v, t a = 0 c to +70 c;industrial: v cc = 3.3v 0.3v, t a = -40 c to +85 c) notes: 1. industrial temperature range product for the 15ns speed grade is available as a standard device. all other speed grades are a vailable by special order. 2. measurements with 0.4 vin vcc. 3. oe v ih, 0.4 v out v cc . 4. tested with outputs disabled (i out = 0). 5. rclk and wclk toggle at 20 mhz and data inputs switch at 10 mhz. 6. typical i cc1 = 0.17 + 0.48*f s + 0.02*c l *f s (in ma) with v cc = 3.3v, t a = 25 c, f s = wclk frequency = rclk frequency (in mhz, using ttl levels), data switching at f s /2, c l = capacitive load (in pf). 7. all inputs = v cc - 0.2v or gnd + 0.2v, except rclk and wclk, which toggle at 20 mhz. absolute maximum ratings (1) note: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v cc terminal only. symbol rating com'l & ind'l unit v term (2) terminal voltage with ?0.5 to +5 v respect to gnd t stg storage temperature ?55 to +125 c i out dc output current ?50 to +50 ma recommended operating conditions symbol parameter min. typ. max. unit v cc supply voltage 3.0 3.3 3.6 v commercial/industrial gnd supply voltage 0 0 0 v v ih input high voltage 2.0 ? 5.5 v commercial/industrial v il input low voltage -0.5 ? 0.8 v commercial/industrial t a operating temperature 0 ? 70 c commercial t a operating temperature -40 ? 85 c industrial
idt72v201/72v211/72v221/72v231/72v241/72v251 3.3v cmos syncfifo? 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 commercial and industrial temperature ranges commercial and industrial temperature ranges february 8, 2006 4 temperature ranges *includes jig and scope capacitances. ac test conditions in pulse levels gnd to 3.0v input rise/fall times 3ns input timing reference levels 1.5v output reference levels 1.5v output load see figure 1 or equivalent circuit figure 1. output load ac electrical characteristics (1) (commercial: v cc = 3.3 0.3v, ta = 0 c to + 70 c;industrial: v cc = 3.3 0.3v, ta = -40 c to + 85 c) notes: 1. pulse widths less than minimum values are not allowed. 2. industrial temperature range is available by special order for speed grades faster than 15ns. 3. values guaranteed by design, not currently tested. commercial com'l & ind'l (2) commercial idt72v201l10 idt72v201l15 idt72v201l20 idt72v211l10 idt72v211l15 idt72v211l20 idt72v221l10 idt72v221l15 idt72v221l20 idt72v231l10 idt72v231l15 idt72v231l20 idt72v241l10 idt72v241l15 idt72v241l20 idt72v251l10 idt72v251l15 idt72v251l20 symbol parameter min. max. min. max. min. max. unit f s clock cycle frequency ? 100 ? 66.7 ? 50 m h z t a data access time 2 6.5 2 10 2 12 ns t clk clock cycle time 10 ? 15 ? 20 ? ns t clkh clock high time 4.5 ? 6 ? 8 ? ns t clkl clock low time 4.5 ? 6 ? 8 ? ns t ds data setup time 3 ? 4 ? 5 ? ns t dh data hold time 0.5 ? 1 ? 1 ? ns t ens enable setup time 3 ? 4 ? 5 ? ns t enh enable hold time 0.5 ? 1 ? 1 ? ns t rs reset pulse width (1) 10 ? 15 ? 20 ? ns t rss reset setup time 8 ? 10 ? 12 ? ns t rsr reset recovery time 8 ? 10 ? 12 ? ns t rsf reset to flag and output time ? 10 ? 15 ? 20 ns t olz output enable to output in low-z (3) 0?0 ?0? ns t oe output enable to output valid 3 ? 3 8 3 10 ns t ohz output enable to output in high-z (3) 3?3 8 310 ns t wff write clock to full flag ? 6.5 ? 10 ? 12 ns t ref read clock to empty flag ? 6.5 ? 10 ? 12 ns t af write clock to almost-full flag ? 6.5 ? 10 ? 12 ns t ae read clock to almost-empty flag ? 6.5 ? 10 ? 12 ns t skew1 skew time between read clock & write 5 ? 6 ? 8 ? ns clock for empty flag &full flag t skew2 skew time between read clock & write 14 ? 18 ? 20 ? ns clock for almost-empty flag & almost-full flag 30pf* d.u.t. 4092 drw03 3.3v 330 ? 510 ?
5 idt72v201/72v211/72v221/72v231/72v241/72v251 3.3v cmos syncfifo? 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 commercial and industrial temperature ranges february 8, 2006 ld wen1 wclk selection 0 0 empty offset (lsb) empty offset (msb) full offset (lsb) full offset (msb) 0 1 no operation 1 0 write into fifo 1 1 no operation figure 2. write offset register notes: 1. for the purposes of this table, wen2 = v ih . 2. the same selection sequence applies to reading from the registers. ren1 and ren2 are enabled and read is performed on the low-to-high transition of rclk. signal descriptions inputs: data in (d0 - d8) data inputs for 9-bit wide data. controls: reset (rs) reset is accomplished whenever the reset ( rs ) input is taken to a low state. during reset, both internal read and write pointers are set to the first location. a reset is required after power-up before a write operation can take place. the full flag ( ff ) and programmable almost-full flag ( paf ) will be reset to high after t rsf . the empty flag ( ef ) and programmable almost-empty flag ( pae ) will be reset to low after t rsf . during reset, the output register is initialized to all zeros and the offset registers are initialized to their default values. write clock (wclk) a write cycle is initiated on the low-to-high transition of the write clock (wclk). data setup and hold times must be met in respect to the low-to-high transition of the write clock (wclk). the full flag (ff) and programmable almost-full flag (paf) are synchronized with respect to the low-to-high transition of the write clock (wclk). the write and read clocks can be asynchronous or coincident. write enable 1 ( wen1 ) if the fifo is configured for programmable flags, write enable 1 ( wen1 ) is the only enable control pin. in this configuration, when write enable 1 ( wen1 ) is low, data can be loaded into the input register and ram array on the low- to-high transition of every write clock (wclk). data is stored in the ram array sequentially and independently of any on-going read operation. in this configuration, when write enable 1 ( wen1 ) is high, the input register holds the previous data and no new data is allowed to be loaded into the register. if the fifo is configured to have two write enables, which allows for depth expansion, there are two enable control pins. see write enable 2 paragraph below for operation in this configuration. to prevent data overflow, the full flag ( ff ) will go low, inhibiting further write operations. upon the completion of a valid read cycle, the full flag ( ff ) will go high after t wff , allowing a valid write to begin. write enable 1 ( wen1 ) is ignored when the fifo is full. read clock (rclk) data can be read on the outputs on the low-to-high transition of the read clock (rclk). the empty flag ( ef ) and programmable almost-empty flag ( pae ) are synchronized with respect to the low-to-high transition of the read clock (rclk). the write and read clocks can be asynchronous or coincident. read enables ( ren1 , ren2 ) when both read enables ( ren1 , ren2 ) are low, data is read from the ram array to the output register on the low-to-high transition of the read clock (rclk). when either read enable ( ren1 , ren2 ) is high, the output register holds the previous data and no new data is allowed to be loaded into the register. when all the data has been read from the fifo, the empty flag ( ef ) will go low, inhibiting further read operations. once a valid write operation has been accomplished, the empty flag ( ef ) will go high after t ref and a valid read can begin. the read enables ( ren1 , ren2 ) are ignored when the fifo is empty. output enable ( oe ) when output enable ( oe ) is enabled (low), the parallel output buffers receive data from the output register. when output enable ( oe ) is disabled (high), the q output data bus is in a high-impedance state. write enable 2/load (wen2/ ld ) this is a dual-purpose pin. the fifo is configured at reset to have programmable flags or to have two write enables, which allows depth expansion. if write enable 2/load (wen2/ ld ) is set high at reset ( rs = low), this pin operates as a second write enable pin. if the fifo is configured to have two write enables, when write enable ( wen1 ) is low and write enable 2/load (wen2/ ld ) is high, data can be loaded into the input register and ram array on the low-to-high transition of every write clock (wclk). data is stored in the ram array sequentially and independently of any on-going read operation. in this configuration, when write enable ( wen1 ) is high and/or write enable 2/load (wen2/ ld ) is low, the input register holds the previous data and no new data is allowed to be loaded into the register. to prevent data overflow, the full flag ( ff ) will go low, inhibiting further write operations. upon the completion of a valid read cycle, the full flag ( ff ) will go high after t wff , allowing a valid write to begin. write enable 1 ( wen1 ) and write enable 2/load (wen2/ ld ) are ignored when the fifo is full. the fifo is configured to have programmable flags when the write enable 2/load (wen2/ ld ) is set low at reset ( rs = low). the idt72v201/72v211/ 72v221/72v231/72v241/72v251 devices contain four 8-bit offset registers which can be loaded with data on the inputs, or read on the outputs. see figure 3 for details of the size of the registers and the default values. if the fifo is configured to have programmable flags when the write enable 1 ( wen1 ) and write enable 2/load (wen2/ ld ) are set low, data on the inputs d is written into the empty (least significant bit) offset register on the first low- to-high transition of the write clock (wclk). data is written into the empty (most significant bit) offset register on the second low-to-high transition of the write clock (wclk), into the full (least significant bit) offset register on the third transition, and into the full (most significant bit) offset register on the fourth transition. the fifth transition of the write clock (wclk) again writes to the empty (least significant bit) offset register. however, writing all offset registers does not have to occur at one time. one or two offset registers can be written and then by bringing the write enable 2/ load (wen2/ ld ) pin high, the fifo is returned to normal read/write operation. when the write enable 2/load (wen2/ ld ) pin is set low, and write enable 1 ( wen1 ) is low, the next offset register in sequence is written. the contents of the offset registers can be read on the output lines when the write enable 2/load (wen2/ ld ) pin is set low and both read enables ( ren1 , ren2 ) are set low. data can be read on the low-to-high transition of the read clock (rclk). a read and write should not be performed simultaneously to the offset registers.
idt72v201/72v211/72v221/72v231/72v241/72v251 3.3v cmos syncfifo? 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 commercial and industrial temperature ranges commercial and industrial temperature ranges february 8, 2006 6 temperature ranges figure 3. offset register location and default values 87 0 empty offset (lsb) reg. default value 007h 80 full offset (lsb) reg. default value 007h 7 80 empty offset (lsb) default value 007h 80 full offset (lsb) default value 007h idt72v201 - 256 x 9-bit idt72v211 - 512 x 9-bit 7 7 80 (msb) 1 00 87 0 empty offset (lsb) reg. default value 007h 80 full offset (lsb) reg. default value 007h 7 87 0 empty offset (lsb) reg. default value 007h 80 full offset (lsb) reg. default value 007h 7 80 empty offset (lsb) default value 007h 80 full offset (lsb) default value 007h idt72v221 - 1,024 x 9-bit idt72v231 - 2,049 x 9-bit idt72v241 - 4,096 x 9-bit 7 7 8080 (msb) 0000 2 (msb) 000 3 80 (msb) 00 1 8080 (msb) 0000 2 (msb) 000 3 80 (msb) 00 1 80 8 0 8 (msb) 1 0 4092 drw 05 80 empty offset (lsb) default value 007h 80 full offset (lsb) default value 007h idt72v251 - 8,192 x 9-bit 7 7 80 (msb) 00000 4 80 (msb) 00000 4
7 idt72v201/72v211/72v221/72v231/72v241/72v251 3.3v cmos syncfifo? 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 commercial and industrial temperature ranges february 8, 2006 outputs: full flag ( ff ) the full flag ( ff ) will go low, inhibiting further write operation, when the device is full. if no reads are performed after reset ( rs ), the full flag ( ff ) will go low after 256 writes for the idt72v201, 512 writes for the idt72v211, 1,024 writes for the idt72v221, 2,048 writes for the idt72v231, 4,096 writes for the idt72v241 and 8,192 writes for the idt72v251. the full flag ( ff ) is synchronized with respect to the low-to-high transition of the write clock (wclk). empty flag ( ef ) the empty flag ( ef ) will go low, inhibiting further read operations, when the read pointer is equal to the write pointer, indicating the device is empty. the empty flag ( ef ) is synchronized with respect to the low-to-high transition of the read clock (rclk). programmable almost-full flag ( paf ) the programmable almost-full flag ( paf ) will go low when the fifo reaches the almost-full condition. if no reads are performed after reset ( rs ), the programmable almost-full flag ( paf ) will go low after (256-m) writes for the idt72v201, (512-m) writes for the idt72v211, (1,024-m) writes for the idt72v221, (2,048-m) writes for the idt72v231, (4,096-m) writes for the idt72v241 and (8,192-m) writes for the idt72v251. the offset ?m? is defined in the full offset registers. if there is no full offset specified, the programmable almost-full flag ( paf ) will go low at full-7 words. the programmable almost-full flag ( paf ) is synchronized with respect to the low-to-high transition of the write clock (wclk). programmable almost-empty flag ( pae ) the programmable almost-empty flag ( pae ) will go low when the read pointer is "n+1" locations less than the write pointer. the offset "n" is defined in the empty offset registers. if no reads are performed after reset the programmable almost-empty flag ( pae ) will go high after "n+1" for the idt72v201/72v211/72v221/72v231/72v241/72v251. if there is no empty offset specified, the programmable almost-empty flag ( pae ) will go low at empty+7 words. the programmable almost-empty flag ( pae ) is synchronized with respect to the low-to-high transition of the read clock (rclk). data outputs (q 0 - q 8 ) data outputs for a 9-bit wide data. number of words in fifo idt72v201 idt72v211 idt72v221 ff paf pae ef 00 0hhll 1 to n (1) 1 to n (1) 1 to n (1) hh lh (n+1) to (256-(m+1)) (n+1) to (512-(m+1)) (n+1) to (1,024-(m+1)) hhhh (256-m) (2) to 255 (512-m) (2) to 511 (1,024-m) (2) to 1,023 h l h h 256 512 1,024 l l h h number of words in fifo idt72v231 idt72v241 idt72v251 ff paf pae ef 000hhll 1 to n (1) 1 to n (1) 1 to n (1) hh lh (n+1) to (2,048-(m+1)) (n+1) to (4,096-(m+1)) (n+1) to (8,192-(m+1)) hhhh (2,048-m) (2) to 2,047 (4,096-m) (2) to 4,095 (8,192-m) (2) to 8,191 h l h h 2,048 4,096 8,192 l l h h notes: 1. n = empty offset (n = 7 default value) 2. m = full offset (m = 7 default value) table 1 ? status flags
idt72v201/72v211/72v221/72v231/72v241/72v251 3.3v cmos syncfifo? 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 commercial and industrial temperature ranges commercial and industrial temperature ranges february 8, 2006 8 temperature ranges notes: 1. holding wen2/ ld high during reset will make the pin act as a second write enable pin. holding wen2/ ld low during reset will make the pin act as a load enable for the programmable flag offset registers. 2. after reset, the outputs will be low if oe = 0 and high-impedance if oe = 1. 3. the clocks (rclk, wclk) can be free-running during reset. figure 4. reset timing note: 1. t skew1 is the minimum time between a rising rclk edge and a rising wclk edge for ff to change during the current clock cycle. if the time between the rising edge of rclk and the rising edge of wclk is less than t skew1 , then ff may not change state until the next wclk edge. figure 5. write cycle timing t rs t rsr rs ren1 , ren2 t rsf t rsf oe = 1 oe = 0 (2) ef , pae ff , paf q 0 - q 8 4092 drw06 wen1 (1) t rss t rsf t rsr t rss t rsr t rss wen2/ ld t dh t enh t skew1 (1) t clk t clkh t clkl t ds t ens t wff t wff wclk d 0 - d 8 wen1 wen2/ (if applicable) ff rclk ren1 , ren2 no operation no operation 4092 drw07 data in valid t enh t ens
9 idt72v201/72v211/72v221/72v231/72v241/72v251 3.3v cmos syncfifo? 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 commercial and industrial temperature ranges february 8, 2006 t ds d 0 (first valid write) t skew1 d 0 d 1 d 3 d 2 d 1 t ens t frl (1) t ref t a t olz t oe t a wclk d 0 - d 8 wen2 (if applicable) rclk ef ren1 , ren2 q 0 - q 8 oe wen1 4092 drw09 t ens t ens note: 1. when t skew1 minimum specification, t frl = t clk + t skew1 when t skew1 < minimum specification, t frl = 2t clk + t skew1 or t clk + t skew1 the latency timings apply only at the empty boundary ( ef = low). figure 7. first data word latency timing t enh t ens no operation t olz valid data t skew1 (1) t clk t clkh t clkl t ref t ref t a t oe t ohz rclk ren1 , ren2 ef q 0 - q 8 oe wclk wen1 wen2 4092 drw08 note: 1. t skew1 is the minimum time between a rising wclk edge and a rising rclk edge for ef to change during the current clock cycle. if the time between the rising edge of rclk and the rising edge of wclk is less than t skew1 , then ef may not change state until the next rclk edge. figure 6. read cycle timing
idt72v201/72v211/72v221/72v231/72v241/72v251 3.3v cmos syncfifo? 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 commercial and industrial temperature ranges commercial and industrial temperature ranges february 8, 2006 10 temperature ranges note: 1. only one of the two write enable inputs, wen1 or wen2 , needs to go inactive to inhibit writes to the fifo. figure 8. full flag timing note: 1. when t skew1 minimum specification, t frl maximum = t clk + t skew1 when t skew1 < minimum specification, t frl maximum = 2t clk + t skew1 or t clk + t skew1 the latency timings apply only at the empty boundary ( ef = low). figure 9. empty flag timing t skew1 t ds t skew1 t enh t enh next data read data read wclk d 0 - d 8 ff wen1 wen2 (if applicable) rclk ren1 , ren2 q 0 - q 8 t wff t wff t wff t ens t ens data in output register oe low no write no write 4092 drw10 t a t a t ens t ens t ens (1) t ens (1) t enh t enh no write t a t ds t ds data write 1 t ens t enh t enh t ens t enh t ens t enh data write 2 wclk d 0 - d 8 rclk ef ren1 , ren2 oe q 0 - q 8 data read t skew1 (1) t frl t ffl data in output register (1) t skew1 low t ens wen2 (if applicable) t ref t ref t ref wen1 4092 drw11
11 idt72v201/72v211/72v221/72v231/72v241/72v251 3.3v cmos syncfifo? 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 commercial and industrial temperature ranges february 8, 2006 notes: 1. m = paf offset. 2. 256 - m words in fifo for idt72v201, 512 - m words for idt72v211, 1,024 - m words for idt72v221, 2,048 - m words for idt72v23 1, 4,096 - m words for idt72v241, 8,192 - m words for idt72v251. 3. t skew2 is the minimum time between a rising rclk edge and a rising wclk edge for paf to change during that clock cycle. if the time between the rising edge of rclk and the rising edge of wclk is less than t skew2 , then paf may not change state until the next wclk rising edge. 4. if a write is performed on this rising edge of the write clock, there will be full - (m-1) words in the fifo when paf goes low. notes: 1. n = pae offset. 2. t skew2 is the minimum time between a rising wclk edge and a rising rclk edge for pae to change during that clock cycle. if the time between the rising edge of wclk and the rising edge of rclk is less than t skew2 , then pae may not change state until the next rclk rising edge. 3. if a read is performed on this rising edge of the read clock, there will be empty + (n-1) words in the fifo when pae goes low. figure 11. programmable empty flag timing figure 10. programmable full flag timing t ens t enh t ens t enh t ens t enh wclk wen1 wen2 (if applicable) paf rclk ren1 , ren2 (4) (1) t paf full - (m + 1) words in fifo full - m words in fifo (2) t clkh t clkl t skew2 (3) t paf 4092 drw12 wclk wen1 wen2 pae rclk ren1 , ren2 t ens t enh t ens t enh t skew2 (2) t ens t enh (if applicable) t pae t pae (3) (1) n words in fifo n + 1 words in fifo t clkh t clkl 4092 drw13
idt72v201/72v211/72v221/72v231/72v241/72v251 3.3v cmos syncfifo? 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 commercial and industrial temperature ranges commercial and industrial temperature ranges february 8, 2006 12 temperature ranges figure 12. write offset registers timing figure 13. read offset registers timing t ens t enh t ens t ds t dh wclk ld wen1 d 0 - d 7 paf offset (msb) paf offset (lsb) pae offset (msb) pae offset (lsb) t clk t clkl t clkh 4092 drw14 t ens t enh t ens data in output register empty offset (lsb) empty offset (msb) full offset (lsb) full offset (msb) rclk ld ren1 , ren2 q 0 - q 7 t clk t a t clkl t clkh 4092 drw15
13 idt72v201/72v211/72v221/72v231/72v241/72v251 3.3v cmos syncfifo? 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 commercial and industrial temperature ranges february 8, 2006 the read enable 2 ( ren2 ) control input can be grounded (see figure 14). in this configuration, the write enable 2/load (wen2/ ld ) pin is set low at reset so that the pin operates as a control to load and read the programmable flag offsets. figure 15. block diagram of 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18 and 8,192 x 18 synchronous fifo used in a width expansion configuration operating configurations single device configuration a single idt72v201/72v211/72v221/72v231/72v241/72v251 may be used when the application requirements are for 256/512/1,024/2,048/4,096/ 8,192 words or less. when these fifos are in a single device configuration, 1,024/2,048/4,096/8,192 words. the existence of two enable pins on the read and write port allow depth expansion. the write enable 2/load pin is used as a second write enable in a depth expansion configuration thus the program- mable flags are set to the default values. depth expansion is possible by using one enable input for system control while the other enable input is controlled by expansion logic to direct the flow of data. a typical application would have the expansion logic alternate data access from one device to the next in a sequential manner. these fifos operate in the depth expansion configuration when the following conditions are met: 1. the wen2/ ld pin is held high during reset so that this pin operates a second write enable. 2. external logic is used to control the flow of data. please see the application note" depth expansion of idt's syn- chronous fifos using the ring counter approach" for details of this configuration. width expansion configuration word width may be increased simply by connecting the corresponding input controls signals of multiple devices. a composite flag should be created for each of the end-point status flags ( ef and ff ). the partial status flags ( ae and af ) can be detected from any one device. figure 15 demonstrates a 18-bit word width by using two idt72v201/72v211/72v221/72v231/72v241/72v251s. any word width can be attained by adding additional idt72v201/72v211/ 72v221/72v231/72v241/72v251s. when these devices are in a width expansion configuration, the read enable 2 ( ren2 ) control input can be grounded (see figure 15). in this configuration, the write enable 2/load (wen2/ ld ) pin is set low at reset so that the pin operates as a control to load and read the programmable flag offsets. depth expansion the idt72v201/72v211/72v221/72v231/72v241/72v251 can be adapted to applications when the requirements are for greater than 256/512/ figure 14. block diagram of single 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 synchronous fifo data out (q 0 - q 8 ) data in (d 0 - d 8 ) reset ( rs ) read clock (rclk) read enable 1 ( ren1 ) output enable ( oe ) empty flag ( ef ) programmable almost-empty ( pae ) read enable 2 ( ren2 ) write clock (wclk) write enable 1 ( wen1 ) write enable 2/load (wen2/ ld ) full flag ( ff ) programmable almost-full ( paf) idt 72v201 72v211 72v221 72v231 72v241 72v251 4092 drw16 data in (d) write clock (wclk) 18 9 9 reset ( rs ) read clock (rclk) data out (q) 9 18 read enable 2 ( ren2 ) read enable 2 ( ren2 ) write enable1 ( wen1 ) full flag ( ff ) #1 programmable ( paf ) programmable ( pae ) empty flag ( ef ) #2 output enable ( oe ) read enable ( ren ) 9 write enable2/load (wen2/ ld ) full flag ( ff ) #2 empty flag ( ef ) #1 reset ( rs ) 4092 drw17 idt 72v201 72v211 72v221 72v231 72v241 72v251 idt 72v201 72v211 72v221 72v231 72v241 72v251
14 corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 408-360-1753 san jose, ca 95138 fax: 408-284-2775 email: fifohelp@idt.com www.idt.com ordering information notes: 1. industrial temperature range product for the 15ns is available as a standard device. all other speed grades are available b y special order. 2. green parts available. for specific speeds and packages contact your sales office. 4092 drw 18 xxxxx idt device type x xx x x power speed package clock cycle time (t clk ) speed in nanoseconds process/ temperature range blank commercial (0 c to +70 c) i (1) industrial (-40 c to +85 c) l low power j plastic leaded chip carrier (plcc, j32-1) pf plastic thin quad flatpack (tqfp, pr32-1) 72v201 256 x 9 ? 3.3v syncfifo ? 72v211 512 x 9 ? 3.3v syncfifo ? 72v221 1,024 x 9 ? 3.3v syncfifo ? 72v231 2,048 x 9 ? 3.3v syncfifo ? 72v241 4,096 x 9 ? 3.3v syncfifo ? 72v251 8,192 x 9 ? 3.3v syncfifo ? 10 15 20 commerical only commerical & industrial commerical only x g green (2) datasheet document history 01/11/2002 pg. 3. 02/01/2002 pg. 3. 02/08/2006 pgs. 1 and 14.

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